The present application relates to a semiconductor integrated circuit and a method of testing delay of the semiconductor integrated circuit, and more particularly, the present application relates to a semiconductor integrated circuit and a method of testing delay of the semiconductor integrated circuit for making it easy to test delay within circuit that includes an area capable of operating at a predetermined clock frequency (hereinafter referred to as “frequency”) and a predetermined voltage and an area capable of operating at frequency and voltage given after shifting among different levels of frequency and different levels of voltage.
Recently, there is being proposed integrated circuit constructed by dividing the interior of semiconductor integrated circuit on a single chip into a plurality of supply voltage and frequency areas and by lowering the level of frequency of area(s) that computes low load tasks accompanied by lowering the level of voltage also of such area(s). That is, this integrated circuit possesses a first area, in which sub-areas, each formed with interior circuits designed to perform various functions, operate at a predetermined frequency and a predetermined voltage, and a second area, which can function at a different level of frequency and a different level of voltage given after shifting among different levels of frequency and different levels of voltage.
As shown in FIG. 9, a semiconductor integrated circuit 1 according to the prior art possesses an A-area 2, which may be regarded as an area (a first area) capable of operating at high frequency and high voltage, and a B-area 3, which may be regarded as a frequency and voltage level shift area (a second area) capable of operating not only at the high frequency and high voltage but also at low frequency and low voltage. In this semiconductor integrated circuit 1, the same frequency and voltage as those used to drive the A-area 2 drive the B-area 3 when it computes heavy load tasks, but, when it computes light load tasks, the frequency driving the B-area 3 and even the voltage are lowered for lowering total power consumption. Accordingly, as shown in FIG. 9, according to the prior art, source voltage area and frequency area are divided from each other by indistinguishable boundary, so named because it disappears when these areas operate at high frequency and high voltage.
As a concrete circuit structure of conventional integrated circuit, as shown in FIG. 10, a combination circuit 12 is provided between registers R3, R4 within A-area 2, which is a first supply-voltage area 1 having a high voltage and a first frequency area 1 having a high frequency, and registers R5, R6 within B-area 3, which is a second supply-voltage area 2 capable of shifting between high and low voltages and a second frequency area 2 capable of shifting between high and low frequencies, and it is provided with a voltage level shifter 13 capable of shifting a voltage level from a high voltage level to a low voltage level and from the low voltage level to the high voltage level.
As a delay trouble-shooting test on semiconductor integrated circuit before shipment, there are a delay test employing scan technique and a field delay test without employing scan technique. The delay test is conducted in the following manner. With semiconductor integrated circuit being driven at a frequency for a delay to be tested, a tester in charge of the test sends digital signal to the semiconductor integrated circuit. Concurrently with the sending of digital signal, the inspector observes digital signal outputted by the semiconductor integrated circuit, and judges that an unacceptable delay has occurred somewhere the signal past so that the semiconductor integrated circuit be rated as a sub-standard article if the digital signal outputted from the semiconductor integrated circuit fails to show a predetermined pattern. The delay test using scan technique is advantageous in that the signal propagation path is easy to specify, making it easy to find where the degraded portion is. However, it is required that all the circuits within an area where the scan is applied be driven at the same frequency. The field delay test without relying on the scan technique is disadvantageous in that the signal propagation path is difficult to specify, making it difficult to find where the degraded portion is if signal outputted from the semiconductor integrated circuit fails to show a predetermined pattern. Conducting the above-mentioned conventional test (delay tests) of semiconductor integrated circuit at the time of shipment will necessarily require testing delay over a delay period between the resistors R3, R4 on the A-area 2 side to define one end of the delay period, and resistors R5, R6 on the B-area 3 side to define the opposite end of the delay period. Tests, performed upon assuming conditions that A-area 2 and B-area 3 are driven at the same frequency, can take the same procedure as the conventional ordinary test of semiconductor integrated circuit requiring no shifting among frequency and voltage.
However, tests, performed upon assuming conditions that, after shifting between different levels of frequency and voltage for B-area 3, different frequency and different voltage from those driving A-area 2 are used to drive B-area, will necessarily require testing delay across a path bridging the A and B-areas against each of all possible combinations of different levels of frequency and voltage needed as an test at the time of shipment, making it necessary to design circuits tough enough to withstand use under each of the all possible combinations of different levels of frequency and voltage.
As mentioned above, the conventional semiconductor integrated circuit, when the first and second areas are driven at different levels of frequency and different levels of source voltage, requires different test vectors for testing delay along signal path bridging frequency and voltage areas, posing a problem of increased time and labor needed for an test at the time of shipment for mass production.